512k x 32 static ram cy7c1062av25 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05333 rev. *a revised july 10, 2006 features ?high speed ?t aa = 10 ns ? low active power ? 745 mw (max.) ? operating voltages of 2.5 0.2v ? 1.5v data retention ? automatic power-down when deselected ? ttl-compatible inputs and outputs ? easy memory expansion with ce 1 , ce 2 , and ce 3 features ? available in non pb-free 119- ball pitch ball grid array package functional description the cy7c1062av25 is a high-performance cmos static ram organized as 524,288 words by 32 bits. writing to the device is accomplished by enabling the chip (ce 1, ce 2 and ce 3 low) and forcing the write enable (we ) input low. if byte enable a (b a ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location specified on the address pins (a 0 through a 18 ). if byte enable b (b b ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 18 ). likewise, b c and b d correspond with the i/o pins i/o 16 to i/o 23 and i/o 24 to i/o 31 , respectively. reading from the device is accomplished by enabling the chip (ce 1, ce 2 , and ce 3 low) while forcing the output enable (oe ) low and write enable (we ) high. if the first byte enable (b a ) is low, then data from the memory location specified by the address pins will appear on i/o 0 to i/o 7 . if byte enable b (b b ) is low, then data from memory will appear on i/o 8 to i/o 15 . similarly, b c and b d correspond to the third and fourth bytes. see the truth table at the back of this data sheet for a complete description of read and write modes. the input/output pins (i/o 0 through i/o 31 ) are placed in a high-impedance state when t he device is deselected (ce 1, ce 2 or ce 3 high), the outputs are disabled (oe high), the byte selects are disabled (b a-d high), or during a write operation (ce 1, ce 2 , and ce 3 low, and we low). the cy7c1062av25 is available in a 119-ball pitch ball grid array (pbga) package. logic block diagram 15 16 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps input buffers 512k x 32 array a 0 a 12 a 14 a 13 a a a 17 a 18 a 10 a 11 i/o 0 ?i/o 31 oe ce 3 b a b d a 9 output buffers control logic b b b c we ce 2 ce 1 [+] feedback [+] feedback
cy7c1062av25 document #: 38-05333 rev. *a page 2 of 9 pin configuration selection guide ?10 unit maximum access time 10 ns maximum operating current com?l/ind?l 275 ma maximum cmos standby current com?l/ind?l 50 ma 234567 1 a b c d e f g h j k l m n p r t u i/o 12 i/o 16 i/o 17 i/o 18 i/o 19 i/o 27 i/o 23 i/o 25 aa aa ai/o 0 aa i/o 21 nc i/o 26 i/o 31 i/o 29 i/o 30 b c v ss v ss v dd v dd a v ss a a v dd ce 2 a ce 1 aai/o 1 nc ce 3 b a i/o 2 v ss v ss v ss v dd i/o 4 i/o 6 v ss v dd v dd v ss i/o 8 a aai/o 15 oe v dd v ss v ss v dd v ss v ss v dd v ss b d v ss v dd v ss v ss i/o 5 v dd v ss v ss v ss dnu v ss v dd v ss v ss v ss v ss v dd v ss v ss i/o 10 v dd i/o 14 i/o 13 a a v ss v ss v ss nc b b v dd i/o 3 we a i/o 20 v ss v dd i/o 22 v dd v ss i/o 7 v dd i/o 9 i/o 11 v dd v dd i/o 24 v ss i/o 28 v ss v dd 119-ball pbga v dd (top view) [+] feedback [+] feedback
cy7c1062av25 document #: 38-05333 rev. *a page 3 of 9 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ?65 c to +150 c ambient temperature with power applied............................................. ?55 c to +125 c supply voltage on v cc relative to gnd [1] .... ?0.5v to +3.6v dc voltage applied to outputs in high-z state [1] ....................................?0.5v to v cc + 0.5v dc input voltage [1] .................................?0.5v to v cc + 0.5v current into outputs (low).... ..................................... 20 ma static discharge voltage......... .............. .............. ....... >2001v (per mil-std-883, method 3015) latch-up current...................................................... >200 ma operating range range ambient temperature v cc commercial 0 c to +70 c 2.5v 0.2v industrial ?40 c to +85 c dc electrical characteristics over the operating range parameter description test conditions ?10 unit min. max. v oh output high voltage v cc = min., i oh = ?1.0 ma 2.0 v v ol output low voltage v cc = min., i ol = 1.0 ma 0.4 v v ih input high voltage 2.0 v cc + 0.3 v v il input low voltage [1] ?0.3 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 a i oz output leakage current gnd < v out < v cc , output disabled ?1 +1 a i cc v cc operating supply current v cc = max., f = f max = 1/t rc com?l/ind?l 275 ma i sb1 automatic ce power-down current?ttl inputs max. v cc , ce > v ih , v in > v ih or v in < v il , f = f max com?l/ind?l 100 ma i sb2 automatic ce power-down current ?cmos inputs max. v cc , ce > v cc ? 0.2v, v in > v cc ? 0.2v, or v in < 0.2v, f = 0 com?l/ind?l 50 ma capacitance [2] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 2.5v 8 pf c out i/o capacitance 10 pf ac test loads and waveforms [3] notes: 1. v il (min.) = ?2.0v for pulse durations of less than 20 ns. 2. tested initially and after any design or process changes that may affect these parameters. 3. valid sram operation does not occur until the power supplies have reached the minimum operating v dd (2.3v). as soon as 1ms (t power ) after reaching the minimum operating v dd , normal sram operation can begin including reduction in v dd to the data retention (v ccdr , 1.5v) voltage. 90% 10% 2.3v gnd 90% 10% all input pulses 2.5v output 5 pf including jig and scope output (a) (b) r1 317 ? 167 ? r2 351 ? venin equivalent th 1.73v rise time > 1 v/ns fall time: > 1 v/ns (c) output 50 ? z 0 = 50 ? v th = v dd /2 30 pf including all components of test equipment [+] feedback [+] feedback
cy7c1062av25 document #: 38-05333 rev. *a page 4 of 9 ac switching characteristics over the operating range [4] parameter description ?10 unit min. max. read cycle t power v cc (typical) to the first access [5] 1 ms t rc read cycle time 10 ns t aa address to data valid 10 ns t oha data hold from address change 3 ns t ace ce 1 , ce 2 , or ce 3 low to data valid 10 ns t doe oe low to data valid 5 ns t lzoe oe low to low-z [6] 1 ns t hzoe oe high to high-z [6] 5 ns t lzce ce 1 , ce 2 , or ce 3 low to low-z [6] 3 ns t hzce ce 1 , ce 2 , or ce 3 high to high-z [6] 5 ns t pu ce 1 , ce 2 , or ce 3 low to power-up [7] 0 ns t pd ce 1 , ce 2 , or ce 3 high to power-down [7] 10 ns t dbe byte enable to data valid 5 ns t lzbe byte enable to low-z [6] 1 ns t hzbe byte disable to high-z [6] 5 ns write cycle [8, 9] t wc write cycle time 10 ns t sce ce 1 , ce 2 , or ce 3 low to write end 7 ns t aw address set-up to write end 7 ns t ha address hold from write end 0 ns t sa address set-up to write start 0 ns t pwe we pulse width 7 ns t sd data set-up to write end 5.5 ns t hd data hold from write end 0 ns t lzwe we high to low-z [6] 3 ns t hzwe we low to high-z [6] 5 ns t bw byte enable to end of write 7 ns notes: 4. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.1v, input pulse levels of 0 to 2. 3v, and output loading of the specified i ol /i oh and transmission line loads. test conditions for the read cycl e use output loading as shown in (a) of ac test loads, unless sp ecified otherwise. 5. this part has a voltage regulator that steps down the voltage from 2.3v to 2v internally. t power time has to be provided initially before a read/write operation is started. 6. t hzoe , t hzce , t hzwe , t hzbe , and t lzoe , t lzce , t lzwe , and t lzbe are specified with a load capacitance of 5 pf as in (b) of ac test loads. transition is measured 200 mv from steady-state voltage. 7. these parameters are guaranteed by design and are not tested. 8. the internal write time of the memory is defined by the overlap of ce 1 low, ce 2 high, ce 3 low, and we low. the chip enables must be active and we must be low to initiate a write, and the transition of any of these signals can terminate the write. the input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 9. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd . [+] feedback [+] feedback
cy7c1062av25 document #: 38-05333 rev. *a page 5 of 9 data retention waveform switching waveforms read cycle no. 1 [11,12] read cycle no. 2 (oe controlled) [11,13] 2.3v 2.3v t cdr v dr > 1.5v data retention mode t r ce v cc previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzbe t pd high oe ce 1 , ce 3 icc i sb impedance address data out v cc supply t dbe t lzbe t hzce b a , b b , b c , b d current i cc ce 2 notes: 10. full device operation requires linear v cc ramp from v dr to v cc(min.) > 100 s or stable at v cc(min.) > 100 s 11. device is continuously selected. oe , ce , b a , b b , b c , b d = v il . 12. we is high for read cycle. 13. address valid prior to or coincident with ce transition low. [+] feedback [+] feedback
cy7c1062av25 document #: 38-05333 rev. *a page 6 of 9 write cycle no. 1 (ce controlled) [14,15,16] write cycle no. 2 (ble or bhe controlled) [14,15,16] notes: 14. ce indicates a combination of all three chip enables. when active low, ce indicates the ce 1 , ce 2 and ce 3 are low. 15. data i/o is high-impedance if oe or b a , b b , b c , b d = v ih . 16. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. switching waveforms t hd t sd t sce t sa t ha t aw t pwe t wc bw datai/o address ce we t b a , b b , b c , b d t hd t sd t bw t sa t ha t aw t pwe t wc t sce datai/o address we ce b a , b b , b c , b d [+] feedback [+] feedback
cy7c1062av25 document #: 38-05333 rev. *a page 7 of 9 write cycle no. 3 (we controlled, oe low) truth table ce 1 ce 2 ce 3 oe we b a b b b c b d i/o 0 ? i/o 7 i/o 8 ? i/o 15 i/o 16 ? i/o 23 i/o 24 ? i/o 31 mode power h h h x x x x x x high-z high-z high-z high-z power down (i sb ) l h l x x x x x x high-z high-z high-z high-z power down (i sb ) l l l l h l l l l data out data out data out data out read all bits (i cc ) l l l l h l h h h data out high-z high-z high-z read byte a bits only (i cc ) l l l l h h l h h high-z data out high-z high-z read byte b bits only (i cc ) l l l l h h h l h high-z high-z data out high-z read byte c bits only (i cc ) l l l l h h h h l high-z high-z high-z data out read byte d bits only (i cc ) l l l x l l l l l data in data in data in data in write all bits (i cc ) l l l x l l h h h data in high-z high-z high-z write byte a bits only (i cc ) l l l x l h l h h high-z data in high-z high-z write byte b bits only (i cc ) l l l x l h h l h high-z high-z data in high-z write byte c bits only (i cc ) l l l x l h h h l high-z high-z high-z data in write byte d bits only (i cc ) l l l h h x x x x high-z high-z high-z high-z selected, outputs disabled (i cc ) switching waveforms t hd t sd t sce t ha t aw t pwe t wc t bw data i/o address ce we t sa t lzwe t hzwe b a , b b , b c , b d [+] feedback [+] feedback
cy7c1062av25 document #: 38-05333 rev. *a page 8 of 9 all product and company names mentioned in this document may be the trademarks of their respective holders. ordering information speed (ns) ordering code package diagram package type operating range 10 CY7C1062AV25-10BGC 51-85115 119-ball plastic ball grid array (14 x 22 x 2.4 mm) commercial cy7c1062av25-10bgi industrial package diagram 51-85115-*b 119-ball pbga (14 x 22 x 2.4 mm) (51-85115) [+] feedback [+] feedback
cy7c1062av25 document #: 38-05333 rev. *a page 9 of 9 document history page document title: cy7c1062av25 512k x 32 static ram document number: 38-05333 rev. ecn no. issue date orig. of change description of change ** 119626 01/29/03 dfp new data sheet *a 493565 see ecn nxr converted from preliminary to final removed -8 and -10 speed bins changed the description of i ix from input load current to input leakage current in dc electrical characteristics table updated the ordering information table [+] feedback [+] feedback
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